MARC details
| 000 -LEADER |
|---|
| fixed length control field |
02486nam a2200241Ia 4500 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
NULRC |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20250520100610.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
250520s9999 xx 000 0 und d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9783642086915 |
| 040 ## - CATALOGING SOURCE |
|---|
| Transcribing agency |
NULRC |
| 050 ## - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
QA 76.9.A73 .M84 2010 |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Mueller, Silvia M. |
| Relator term |
author |
| 245 #0 - TITLE STATEMENT |
|---|
| Title |
Computer architecture : |
| Remainder of title |
complexity and correctness / |
| Statement of responsibility, etc. |
Silvia M. Mueller and Wolfgang J. Paul. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
Berlin : |
| Name of publisher, distributor, etc. |
Springer, |
| Date of publication, distribution, etc. |
c2010 |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xiii, 553 pages : |
| Other physical details |
illustrations ; |
| Dimensions |
24 cm. |
| 365 ## - TRADE PRICE |
|---|
| Price amount |
USD125.59 |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc. note |
Includes bibliographical references (pages 543-547) and index. |
| 505 ## - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
1 Introduction.- 2 Basics.- 3 A Sequential DLX Design.- 4 Basic Pipelining.- 5 Interrupt Handling.- 6 Memory System Design.- 7 IEEE Floating Point Standard and Theory of Rounding.- 8 Floating Point Algorithms and Data Paths.- 9 Pipelined DLX Machine with Floating Point Core.- A DLX Instruction Set Architecture.- A.1 DLX Fixed-Point Core: FXU.- A.1.1 Instruction Formats.- A.1.2 Instruction Set Coding.- A.2 Floating-Point Extension.- A.2.1 FPU Register Set.- A.2.2 FPU Instruction Set.- B Specification of the FDLX Design.- B.1 RTL Instructions of the FDLX.- B.1.l Stage IF.- B.1.2 Stage ID.- B.1.3 Stage EX.- B.1.4 Stage M.- B.1.5 Stage WB.- B.2 Control Automata of the FDLX Design.- B.2.1 Automaton Controlling Stage ID.- B.2.2 Precomputed Control. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
"Computer Architecture: Complexity and Correctness develops, at the gate level, the complete design of a pipelined RISC processor with delayed branch, forwarding, hardware interlock, precise maskable nested interrupts, caches, and a fully IEEE-compliant floating point unit. In contrast to other design approaches applied in practice and unlike other textbooks available, the design presented here are modular, clean and complete up to the construction of entire complex machines. The authors' systematically basing their approach on rigorous mathematical formalisms allows for rigorous correctness proofs, accurate hardware costs determination, and performance evaluation as well as, generally speaking, for coverage of a broad variety of relevant issues within a reasonable number of pages. The book is written as a text for classes on computer architecture and related topics and will serve as a valuable source of reference for professionals in hardware design."--Publisher's website |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
COMPUTER ARCHITECTURE |
| 700 ## - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Paul, Wolfgang J. |
| Relator term |
co-author |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
Library of Congress Classification |
| Koha item type |
Books |
