MARC details
| 000 -LEADER |
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| fixed length control field |
02100nam a2200241Ia 4500 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
NULRC |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20250520100610.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
250520s9999 xx 000 0 und d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9780521769921 |
| 040 ## - CATALOGING SOURCE |
|---|
| Transcribing agency |
NULRC |
| 050 ## - LIBRARY OF CONGRESS CALL NUMBER |
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| Classification number |
QA 76.5 .B34 2010 |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Baer, Jean-Loup. |
| Relator term |
author |
| 245 #0 - TITLE STATEMENT |
|---|
| Title |
Microprocessor architecture : |
| Remainder of title |
from simple pipilines to chip multiprocessors / |
| Statement of responsibility, etc. |
Jean-Loup Baer |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
Cambridge : |
| Name of publisher, distributor, etc. |
Cambridge University Press, |
| Date of publication, distribution, etc. |
c2010 |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xiv, 367 pages : |
| Other physical details |
illustrations ; |
| Dimensions |
26 cm. |
| 365 ## - TRADE PRICE |
|---|
| Price amount |
USD57.73 |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc. note |
Includes bibliographical references and index. |
| 505 ## - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Introduction -- The basics -- Superscalar processors -- Front-end : branch predictio, instruction fetching, and register renaming -- Back-end : instruction scheduling, memory access instructions, and clusters -- The cache hierarchy -- Multiprocessors -- Multithreading and (chip) multiprocessing -- Current limitations and future challenges. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
This book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars. It discusses topics such as: • The policies and mechanisms needed for out-of-order processing such as register renaming, reservation stations, and reorder buffers • Optimizations for high performance such as branch predictors, instruction scheduling, and load-store speculations • Design choices and enhancements to tolerate latency in the cache hierarchy of single and multiple processors • State-of-the-art multithreading and multiprocessing emphasizing single chip implementations Topics are presented as conceptual ideas, with metrics to assess the performance impact, if appropriate, and examples of realization. The emphasis is on how things work at a black box and algorithmic level. The author also provides sufficient detail at the register transfer level so that readers can appreciate how design features enhance performance as well as complexity. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
MICROPROCESSORS |
| 700 ## - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Baer, Jean-Loup. |
| Relator term |
co-author |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
Library of Congress Classification |
| Koha item type |
Books |
