MARC details
| 000 -LEADER |
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| fixed length control field |
07430nam a2200241Ia 4500 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
NULRC |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20250520102709.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
250520s9999 xx 000 0 und d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9780134101613 |
| 040 ## - CATALOGING SOURCE |
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| Transcribing agency |
NULRC |
| 050 ## - LIBRARY OF CONGRESS CALL NUMBER |
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| Classification number |
QA 76.9.C643 .S73 2016 |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
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| Personal name |
Stallings, William. |
| Relator term |
author |
| 245 #0 - TITLE STATEMENT |
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| Title |
Computer organization and architecture : |
| Remainder of title |
designing for performance / |
| Statement of responsibility, etc. |
William Stallings |
| 250 ## - EDITION STATEMENT |
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| Edition statement |
Tenth Edition. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
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| Place of publication, distribution, etc. |
Boston, Massachusetts : |
| Name of publisher, distributor, etc. |
Pearson Education Limited, |
| Date of publication, distribution, etc. |
c2016 |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xxiii, 833 pages : |
| Other physical details |
color illustrations ; |
| Dimensions |
24 cm. |
| 365 ## - TRADE PRICE |
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| Price amount |
USD260.73 |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
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| Bibliography, etc. note |
Includes bibliographical references (pages 800-808) and index. |
| 505 ## - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
Machine generated contents note: ch. 1 Basic Concepts and Computer Evolution -- 1.1. Organization and Architecture -- 1.2. Structure and Function -- 1.3. Brief History of Computers -- 1.4. Evolution of the Intel x86 Architecture -- 1.5. Embedded Systems -- 1.6. Arm Architecture -- 1.7. Cloud Computing -- 1.8. Key Terms, Review Questions, and Problems -- ch. 2 Performance Issues -- 2.1. Designing for Performance -- 2.2. Multicore, Mics, and GPGPUs -- 2.3. Two Laws that Provide Insight: Ahmdahl's Law and Litde's Law -- 2.4. Basic Measures of Computer Performance -- 2.5. Calculating the Mean -- 2.6. Benchmarks and Spec -- 2.7. Key Terms, Review Questions, and Problems -- ch. 3 Top-Level View of Computer Function and Interconnection -- 3.1. Computer Components -- 3.2. Computer Function -- 3.3. Interconnection Structures -- 3.4. Bus Interconnection -- 3.5. Point-to-Point Interconnect -- 3.6^ PCI Express -- 3.7. Key Terms, Review Questions, and Problems -- ch. 4 Cache Memory -- 4.1. Computer Memory System Overview -- 4.2. Cache Memory Principles -- 4.3. Elements of Cache Design -- 4.4. Pentium 4 Cache Organization -- 4.5. Key Terms, Review Questions, and Problems -- Appendix 4A Performance Characteristics of Two-Level Memories -- ch. 5 Internal Memory -- 5.1. Semiconductor Main Memory -- 5.2. Error Correction -- 5.3. DDR DRAM -- 5.4. Flash Memory -- 5.5. Newer Nonvolatile Solid-State Memory Technologies -- 5.6. Key Terms, Review Questions, and Problems -- ch. 6 External Memory -- 6.1. Magnetic Disk -- 6.2. RAID -- 6.3. Solid State Drives -- 6.4. Optical Memory -- 6.5. Magnetic Tape -- 6.6. Key Terms, Review Questions, and Problems -- ch. 7 Input/Output -- 7.1. External Devices -- 7.2. I/O Modules -- 7.3. Programmed I/O -- 7.4. Interrupt-Driven I/O -- 7.5^6^ Direct Memory Access -- 7.6. Direct Cache Access -- 7.7. I/O Channels and Processors -- 7.8. External Interconnection Standards -- 7.9. IBM zEnterprise EC12 I/O Structure -- 7.10. Key Terms, Review Questions, and Problems -- ch. 8 Operating System Support -- 8.1. Operating System Overview -- 8.2. Scheduling -- 8.3. Memory Management -- 8.4. Intel x86 Memory Management -- 8.5. Arm Memory Management -- 8.6. Key Terms, Review Questions, and Problems -- ch. 9 Number Systems -- 9.1. Decimal System -- 9.2. Positional Number Systems -- 9.3. Binary System -- 9.4. Converting Between Binary and Decimal -- 9.5. Hexadecimal Notation -- 9.6. Key Terms and Problems -- ch. 10 Computer Arithmetic -- 10.1. Arithmetic and Logic Unit -- 10.2. Integer Representation -- 10.3. Integer Arithmetic -- 10.4. Floating-Point Representation -- 10.5. Floating-Point Arithmetic -- 10.6^iven I/O -- 7.5^6^ Key Terms, Review Questions, and Problems -- ch. 11 Digital Logic -- 11.1. Boolean Algebra -- 11.2. Gates -- 11.3. Combinational Circuits -- 11.4. Sequential Circuits -- 11.5. Programmable Logic Devices -- 11.6. Key Terms and Problems -- ch. 12 Instruction Sets: Characteristics and Functions -- 12.1. Machine Instruction Characteristics -- 12.2. Types of Operands -- 12.3. Intel x86 and ARM Data Types -- 12.4. Types of Operations -- 12.5. Intel x86 and ARM Operation Types -- 12.6. Key Terms, Review Questions, and Problems -- Appendix 12A Little-, Big-, and Bi-Endian -- ch. 13 Instruction Sets: Addressing Modes and Formats -- 13.1. Addressing Modes -- 13.2. x86 and ARM Addressing Modes -- 13.3. Instruction Formats -- 13.4. x86 and ARM Instruction Formats -- 13.5. Assembly Language -- 13.6. Key Terms, Review Questions, and Problems -- ch. 14 Processor Structure and Function -- 14.1^7.5^6^ Processor Organization -- 14.2. Register Organization -- 14.3. Instruction Cycle -- 14.4. Instruction Pipelining -- 14.5. x86 Processor Family -- 14.6. ARM Processor -- 14.7. Key Terms, Review Questions, and Problems -- ch. 15 Reduced Instruction Set Computers -- 15.1. Instruction Execution Characteristics -- 15.2. Use of a Large Register File -- 15.3. Compiler-Based Register Optimization -- 15.4. Reduced Instruction Set Architecture -- 15.5. RISC Pipelining -- 15.6. MIPS R4000 -- 15.7. SPARC -- 15.8. RISC versus CISC Controversy -- 15.9. Key Terms, Review Questions, and Problems -- ch. 16 Instruction-Level Parallelism and Superscalar Processors -- 16.1. Overview -- 16.2. Design Issues -- 16.3. Intel Core Microarchitecture -- 16.4. ARM Cortex-A8 -- 16.5. ARM Cortex-M3 -- 16.6. Key Terms, Review Questions, and Problems -- ch. 17 Parallel Processing -- 17.1^nction -- 14.1^7.5^6^ Multiple Processor Organizations -- 17.2. Symmetric Multiprocessors -- 17.3. Cache Coherence and the MESI Protocol -- 17.4. Multithreading and Chip Multiprocessors -- 17.5. Clusters -- 17.6. Nonuniform Memory Access -- 17.7. Cloud Computing -- 17.8. Key Terms, Review Questions, and Problems -- ch. 18 Multicore Computers -- 18.1. Hardware Performance Issues -- 18.2. Software Performance Issues -- 18.3. Multicore Organization -- 18.4. Heterogeneous Multicore Organization -- 18.5. Intel Core i7-990X -- 18.6. ARM Cortex-A15 MPCore -- 18.7. IBM zEnterprise EC12 Mainframe -- 18.8. Key Terms, Review Questions, and Problems -- ch. 19 General-Purpose Graphic Processing Units -- 19.1. Cuda Basics -- 19.2. GPU versus CPU -- 19.3. GPU Architecture Overview -- 19.4. Intel's Gen8 GPU -- 19.5. When to Use a GPU as a Coprocessor -- 19.6. Key Terms and Review Questions -- ch. 20 Control Unit Operation^^^ 20.1. Micro-Operations -- 20.2. Control of the Processor -- 20.3. Hardwired Implementation -- 20.4. Key Terms, Review Questions, and Problems -- ch. 21 Microprogrammed Control -- 21.1. Basic Concepts -- 21.2. Microinstruction Sequencing -- 21.3. Microinstruction Execution -- 21.4. TI 8800 -- 21.5. Key Terms, Review Questions, and Problems -- A.1. Interactive Simulations -- A.2. Research Projects -- A.3. Simulation Projects -- A.4. Assembly Language Projects -- A.5. Reading/Report Assignments -- A.6. Writing Assignments -- A.7. Test Bank -- B.1. Assembly Language -- B.2. Assemblers -- B.3. Loading and Linking -- B.4. Key Terms, Review Questions, and Problems. |
| 520 ## - SUMMARY, ETC. |
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| Summary, etc. |
Computer Organization and Architecture is a comprehensive coverage of the entire field of computer design updated with the most recent research and innovations in computer structure and function. With clear, concise, and easy-to-read material, the Tenth Edition is a user-friendly source for people studying computers. Subjects such as I/O functions and structures, RISC, and parallel processors are explored integratively throughout, with real world examples enhancing the text for reader interest. With brand new material and strengthened pedagogy, this text engages readers in the world of computer organization and architecture. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
COMPUTER ORGANIZATION |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
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| Source of classification or shelving scheme |
Library of Congress Classification |
| Koha item type |
Books |
